The present invention relates to a MOS type semiconductor memory device constituted with MOS transistors and, particularly, to a MOS type semiconductor memory device having a redundancy function and transistors for resetting word lines.
In a MOS type semiconductor memory device (MOS memory) such as DRAM or SRAM, etc., a number of memory cells are arranged in a matrix form of rows (X) and colums (Y), word lines for selecting memory cells in the respective rows are arranged in the row direction and digit lines for transmitting data of memory cells in the respective columns are arranged in the column direction. For a reset period, the word lines are set at a reference potential such as ground potential through word line resetting transistors. In this case, the respective digit lines have been precharged to a predetermined voltage. For an active period, only one word line is selected and its potential is raised to a power source level. The remaining word lines are connected through the word line resetting transistors to the reference potential.
In a MOS memory constructed as mentioned above, it is assumed that there is a defective column and there is a leak current path between a digit line and a word line in the defective column. In this case, the function of the MOS memory is maintained by substituting a redundant column provided preliminarily for the defective column. However, since, in this case, the digit line in the defective column is still precharged, a current flows from the precharge power source through the leak current path, the word line and the resetting transistor to the reference potential during the reset period, causing power consumption during resetting (stand-by period) to be increased.